Current Issue : April - June Volume : 2017 Issue Number : 2 Articles : 5 Articles
A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Auto gain Control Loop (AGC)\nin hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes\nstatistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented\nwith 0.13...
An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW)\nsensors. In this paper, we present a low-noise complementary metalââ?¬â??oxideââ?¬â??semiconductor (CMOS)\nreadout application-specific integrated circuit (ASIC) based on an SAWsensor array for achieving\na miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately\n114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency\nreadout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was\nfabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 Ã?¼m 1P6M CMOS process\ntechnology. The total chip size was nearly 1203 Ã?â?? 1203 Ã?¼m2. The chip was operated at a supply\nvoltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference\nbetween frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and\nethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption\nlevels of the analog and digital circuits were 1.742 mW and 761 Ã?¼W, respectively....
This paper proposes FuMicro, a fused microarchitecture integrating both in-order superscalar and Very Long Instruction Word\n(VLIW) in a single core. A processor with FuMicro microarchitecture can work under alternative in-order superscalar and VLIW\nmode, using the same pipeline and the same Instruction Set Architecture (ISA). Small modification to the compiler is made to\nexpand the register file in VLIW mode.The decision of mode switch is made by software, and this does not need extra hardware.\nVLIW code can be exploited in the form of library function and the users will be exposed under only superscalar mode; by this\nmeans,we can provide the users with a convenient development environment. FuMicro could serve as a universal microarchitecture\nfor it can be applied to different ISAs. In this paper, we focus on the implementation of FuMicro with ARM ISA. This architecture\nis evaluated on gem5, which is a cycle accurate microarchitecture simulation platform. By adopting FuMicro microarchitecture,\nthe performance can be improved on an average of 10%, with the best performance improvement being 47.3%, compared with that\nunder pure in-order super scalar mode. The result shows that FuMicro microarchitecture can improve Instruction Level Parallelism\n(ILP) significantly, making it promising to expand digital signal processing capability on a General Purpose Processor....
In the large-scale high energy physics and astrophysics experiments multi-channel\nreadout application specific integrated circuits (ASICs) are widely used. The ASICs for such\nexperiments are complicated systems, which usually include both analog and digital building\nblocks. The complexity and large number of channels in such ASICs require the proper\nmethodological approach to their design. The paper represents the mixed-signal design flow of\nthe ASICs for high energy physics and cosmic rays experiments. This flow was successfully\nembedded to the development of the read-out ASIC prototype for the muon chambers of the\nCBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The\ndesign flow enable to analyse the mixed-signal system operation on the different levels:\nfunctional, behavioural, schematic and post layout including parasitic elements. The proposed\ndesign flow allows reducing the simulation period and eliminating the functionality\nmismatches on the very early stage of the design....
The prolonged operation of semiconductor integrated circuits (ICs) needed for\nlong-duration exploration of the surface of Venus has proven insurmountably challenging\nto date due to the âË?¼ 460 ââ??¦C, âË?¼ 9.4 MPa caustic environment. Past and\nplanned Venus landers have been limited to a few hours of surface operation, even\nwhen IC electronics needed for basic lander operation are protected with heavily\ncumbersome pressure vessels and cooling measures. Here we demonstrate vastly\nlonger (weeks) electrical operation of two silicon carbide (4H-SiC) junction field\neffect transistor (JFET) ring oscillator ICs tested with chips directly exposed (no\ncooling and no protective chip packaging) to a high-fidelity physical and chemical\nreproduction of Venusââ?¬â?¢ surface atmosphere. This represents more than 100-fold\nextension of demonstrated Venus environment electronics durability. With further\ntechnology maturation, such SiC IC electronics could drastically improve Venus lander\ndesigns and mission concepts, fundamentally enabling long-duration enhanced\nmissions to the surface of Venus...
Loading....